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1 for more information www.linear.com/ltc6268 typical application features description 500mhz ultra-low bias current fet input op amp the lt c ? 6268/ltc6269 is a single / dual 500 mhz fet - input operational amplifier with extremely low input bias current and low input capacitance. it also features low input- referred current noise and voltage noise making it an ideal choice for high speed transimpedance amplifiers, ccd output buffers, and high-impedance sensor amplifiers. its low distortion makes the ltc6268/ltc6269 an ideal amplifier for driving sar adcs. it operates on 3.1v to 5.25v supply and consumes 16.5ma per amplifier. a shutdown feature can be used to lower power consumption when the amplifier is not in use. the ltc6268 single op amp is available in 8- lead soic and 6-lead sot-23 packages. the soic package includes two unconnected pins which can be used to create an input pin guard ring to protect against board leakage currents. the ltc6269 dual op amp is available in 8- lead msop with exposed pad and 3mm 3mm 10- lead dfn packages. they are fully specified over the C40 c to 85 c and the C40c to 125c temperature ranges. 20k tia frequency response 20k gain 65mhz trans-impedance amplifier applications n gain bandwidth product: 500mhz n C3db bandwidth (a = 1): 350mhz n low input bias current: 3 fa typ. room temperature 4 pa max at 125c n current noise (100khz): 5.5fa/hz n voltage noise (1mhz): 4.3nv/hz n extremely low c in 450ff n rail-to-rail output n slew rate: 400v/s n supply range: 3.1v to 5.25v n quiescent current: 16.5ma n harmonic distortion (2v p-p ): C100 db at 1mhz C80 db at 10mhz n operating temp range: C40c to 125c n single in 8-lead so-8, 6-lead tsot-23 packages n dual in 8-lead ms8, 3 mm 3 mm 10-lead dfn 10 packages n trans-impedance amplifiers n adc drivers n ccd output buffer n photomultiplier t ube post-amplifier n low i bias circuits l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. + ? ltc6268 6268 ta01 2.5v parasitic feedback c 2.5v pd ?2.5v v out = ?i pd ? 20k bw = 65mhz pd = osi optoelectronics, fci-125g-006 *two 40.2k 0603 package resistors in parallel 20k* i pd frequency (mhz) 0.01 40 gain (db) 90 80 70 60 50 100 10 100 1000 0.1 1 6268 ta02 ltc 6268/ ltc 6269 62689f
2 for more information www.linear.com/ltc6268 pin configuration absolute maximum ratings supply voltage v + to v C ........................................... 5. 5 v input voltage ............................... v C C 0.2 v to v + + 0.2 v input current (+ in , C in )( note 2) ............................ 1 ma in put current ( shdn ) ............................................ 1 ma o utput current (i out ) ( note 8, 9) ......................... 13 5 ma output short - circuit duration ( note 3) ... the rmally limited operating temperature range ltc 6 268 i/ ltc 6269 i ............................. C 40 c to 85 c ltc 6 268 h/ ltc 6269 h ........................ C 40 c to 125 c (note 1) 1 2 3 4 8 7 6 5 top view shdn v + out v ? nc ?in +in nc s8 package 8-lead plastic so t jmax = 150c, ja = 120c/w (note 5) 1 2 3 6 5 4 top view s6 package 6-lead plastic tsot-23 v + shdn ?in out v ? +in t jmax = 150c, ja = 192c/w (note 5) 1 2 3 4 outa ?ina +ina v ? 8 7 6 5 v + outb ?inb +inb top view ms8e package 8-lead plastic msop 9 v ? t jmax = 150c, ja = 40c/w (note 5) exposed pad (pin 9) is v C , it is recommended to solder to pcb top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v+ outb ?inb +inb sdb outa ?ina +ina v ? sda 11 v ? t jmax = 150c, ja = 43c/w (note 5) exposed pad (pin 11) is v C , it is recommended to solder to pcb specified temperature range ( note 4) ltc 6 268 i/ ltc 6269 i ............................. C 40 c to 85 c ltc 6 268 h/ ltc 6269 h ........................ C 40 c to 125 c maximum junction temperature .......................... 15 0 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ................... 30 0 c ltc 6268/ ltc 6269 62689f
3 for more information www.linear.com/ltc6268 order information lead free finish tape and reel part marking* package description specified temperature range ltc6268is6#trmpbf ltc6268is6#trpbf ltgfs 6-lead plastic tsot-23 C40c to 85c ltc6268hs6#trmpbf ltc6268hs6#trpbf ltgfs 6-lead plastic tsot-23 C40c to 125c ltc6268is8#pbf ltc6268is8#trpbf 6268 8-lead plastic soic C40c to 85c ltc6268hs8#pbf ltc6268hs8#trpbf 6268 8-lead plastic soic C40c to 125c ltc6269ims8e#pbf ltc6269ims8e#trpbf ltgfp 8-lead plastic msop C40c to 85c ltc6269hms8e#pbf ltc6269hms8e#trpbf ltgfp 8-lead plastic msop C40c to 125c ltc6269idd#pbf ltc6269idd#trpbf lgfn 10-lead plastic dd C40c to 85c ltc6269hdd#pbf ltc6269hdd#trpbf lgfn 10-lead plastic dd C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units v os input offset voltage v cm = 2.75v l C0.7 C2.5 0.2 0.7 2.5 mv mv v cm = 4.0v l C1.0 C4.5 0.2 1.0 4.5 mv mv tc v os input offset voltage drift v cm = 2.75v 4 v/c i b input bias current (notes 6, 8) v cm = 2.75v ltc6268i/ltc6269i ltc6268h/ltc6269h l l C20 C900 C4 3 20 900 4 fa fa pa v cm = 4.0v ltc6268i/ltc6269i ltc6268h/ltc6269h l l C20 C900 C4 3 20 900 4 fa fa pa i os input offset current (notes 6, 8) v cm = 2.75v ltc6268i/ltc6269i ltc6268h/ltc6269h l l C40 C450 C2 6 40 450 2 fa fa pa e n input voltage noise density, v cm = 2.75v f = 1mhz 4.3 nv/hz input voltage noise density, v cm = 4.0v f = 1mhz 4.9 nv/hz input referred noise voltage f = 0.1hz to 10hz 13 v p-p i n input current noise density, v cm = 2.75v f = 100khz 5.5 fa/hz input current noise density, v cm = 4.0v f = 100khz 5.3 fa/hz r in input resistance differential >1000 g common mode >1000 g c in input capacitance differential (dc to 200mhz) 100 ff common mode (dc to 100mhz) 450 ff cmrr common mode rejection ratio v cm = 0.5v to 3.2v (pnp side) l 72 70 90 db db v cm = 0v to 4.5v l 64 52 82 db db ivr input voltage range guaranteed by cmrr l 0 4.5 v the l denotes specifications that apply over the full operating temp erature range, otherwise specifications are at t a = 25c, v supply = 5.0v (v + = 5v, v C = 0v, v cm = mid-supply), r l = 1k, c l = 10pf, v shdn is unconnected. 5.0 v electrical characteristics ltc 6268/ ltc 6269 62689f
4 for more information www.linear.com/ltc6268 the l denotes specifications that apply over the full operating temp erature range, otherwise specifications are at t a = 25c, v supply = 5.0v (v + = 5v, v C = 0v, v cm = mid-supply), r l = 1k, c l = 10pf, v shdn is unconnected. symbol parameter conditions min typ max units psrr power supply rejection ratio v cm = 1.0v, v supply ranges from 3.1v to 5.25v l 78 75 95 db db supply voltage range l 3.1 5.25 a v open loop voltage gain v out = 0.5v to 4.5v r load = 10k l 125 40 250 v /mv v/mv r load = 100 l 10 2 21 v /mv v/mv v ol output swing low (input overdrive 30mv) measured from v C i sink = 10ma l 80 140 200 mv mv i sink = 25ma l 130 200 260 mv mv v oh output swing high (input overdrive 30mv) measured from v + i source = 10ma l 70 140 200 mv mv i source = 25ma l 160 270 370 mv mv i sc output short circuit current (note 9) l 60 40 90 ma ma i s supply current per amplifier l 15 9 16.5 18 23 ma ma supply current in shutdown (per amplifier) l 0.39 0.85 1.2 ma ma i shdn shutdown pin current v shdn = 0.75v v shdn =1.50v l l C12 C12 2 2 12 12 a a v il shdn input low voltage disable l 0.75 v v ih shdn input high voltage enable. if shdn is unconnected, amp is enabled l 1.5 v t on turn on time, delay from shdn toggle to output reaching 90% of target shdn toggle from 0v to 2v, a v = 1 580 ns t off turn off time, delay from shdn toggle to output high z shdn toggle from 2v to 0v, a v = 1 480 ns bw C3db closed loop bandwidth a v = 1 350 mhz gbw gain-bandwidth product f = 10mhz 400 500 mhz t s settling time, 1v to 4v, unity gain 0.1% 17 ns sr+ slew rate+ a v = 6 (r f = 499, r g = 100) v out = 0.5v to 4.5v, measured 20% to 80%, c load = 10pf l 300 200 400 v/s v/s sr C slew rateC a v = 6 (r f = 499, r g = 100) v out = 4.5v to 0.5v, measured 80% to 20%, c load = 10pf l 180 130 260 v/s v/s fpbw full power bandwidth (note 7) 4v p-p 21 mhz hd harmonic distortion(hd2/hd3) a = 1, 10mhz. 2v p-p , v cm = 1.75v, r l = 1k C81/C90 db thd+n total harmonic distortion and noise a = 1, 10mhz. 2v p-p , v cm = 1.75v, r l = 1k 0.01 C79.6 % db i leak output leakage current in shutdown v shdn = 0v, v out = 0v v shdn = 0v, v out = 5v 400 400 na na 5.0 v electrical characteristics ltc 6268/ ltc 6269 62689f
5 for more information www.linear.com/ltc6268 3.3 v electrical characteristics the l denotes specifications that apply over the full operating temp erature range, otherwise specifications are at t a = 25c, v supply = 3.3v (v + = 3.3v, v C = 0v, v cm = mid-supply), r l = 1k, c l = 10pf, v shdn is unconnected. symbol parameter conditions min typ max units v os input offset voltage v cm = 1.0v l C0.7 C2.5 0.2 0.7 2.5 mv mv v cm = 2.3v l C1.0 C4.5 0.2 1.0 4.5 mv mv tc v os input offset voltage drift v cm = 1.0v 4 v/c i b input bias current (notes 6, 8) v cm = 1.0v ltc6268i/ltc6269i ltc6268h/ltc6269h l l C20 C900 C4 3 20 900 4 fa fa pa v cm = 2.3v ltc6268i/ltc6269i ltc6268h/ltc6269h l l C20 C900 C4 3 20 900 4 fa fa pa i os input offset current (notes 6, 8) v cm = 1.0v ltc6268i/ltc6269i ltc6268h/ltc6269h l l C40 C450 C2 6 40 450 2 fa fa pa e n input voltage noise density, v cm =1.0v f = 1mhz 4.3 nv/hz input voltage noise density, v cm = 2.3 v f = 1mhz 4.9 nv/hz input referred noise voltage f = 0.1hz to 10hz 13 v p-p i n input current noise density, v cm = 1.0 v f = 100khz 5.6 fa/hz input current noise density, v cm = 2.3 v f = 100khz 5.3 fa/hz r in input resistance differential common mode >1000 >1000 g g c in input capacitance differential (dc to 200mhz) common mode (dc to 100mhz) 100 450 ff ff cmrr common mode rejection ratio v cm = 0.5v to 1.2v (pnp side) l 63 60 100 db db v cm = 0v to 2.8v (full range) l 60 50 77 db db ivr input v oltage range guaranteed by cmrr l 0 2.8 v a v open loop voltage gain v out = 0.5v to 2.8v r load = 10k l 80 40 200 v /mv v/mv r load = 100 l 10 2 18 v /mv v/mv v ol output swing low (input overdrive 30mv). measured from v C i sink = 10ma l 80 140 200 mv mv i sink = 25ma l 140 200 260 mv mv v oh output swing high (input overdrive 30mv). measured from v + i source = 10ma l 80 140 200 mv mv i source = 25ma l 170 270 370 mv mv i sc output short circuit current (note 9) l 50 35 80 ma ma i s supply current per amplifier l 14.5 9 16 17.5 23 ma ma ltc 6268/ ltc 6269 62689f
6 for more information www.linear.com/ltc6268 symbol parameter conditions min typ max units supply current in shutdown (per amplifier) l 0.23 0.6 0.8 ma ma i shdn shutdown pin current v shdn = 0.75v v shdn = 1.5v l l C12 C12 2 2 12 12 a a v il shdn input low voltage disable l 0.75 v v ih shdn input high voltage enable. if shdn is unconnected, amp is enabled l 1.5 v t on turn on time, delay from shdn toggle to output reaching 90% of target shdn toggle from 0v to 2v 710 ns t off turn off time, delay from shdn toggle to output high z shdn toggle from 2v to 0v 620 ns bw C3db closed loop bandwidth a v = 1 350 mhz gbw gain-bandwidth product f = 10mhz 370 420 mhz sr+ slew rate+ a v = 6 (r f = 499, r g = 100), v out = 0.5v to 2.8v, measured 20% to 80%, c load = 10pf l 300 200 400 v/s v/s sr C slew rateC a v = 6 (r f = 499, r g = 100), v out = 2.8v to 0.5v, measured 80% to 20%, c load = 10pf l 180 130 260 v/s v/s fpbw full power bandwidth (note 7) 2v p-p 40 mhz hd harmonic distortion(hd2/hd3) a = 1, 10mhz. 1v p-p , v cm = 1.65v, r l = 1k C81/C90 db thd+n total harmonic distortion and noise a = 1, 10mhz. 1v p-p , v cm = 1.65v, r l = 1k 0.01 C78 % db 3.3 v electrical characteristics the l denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25c, v supply = 3.3v (v + = 3.3v, v C = 0v, v cm = mid-supply) r l = 1k, c l = 10pf, v shdn is unconnected. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs are protected by two series connected esd protection diodes to each power supply. the input current should be limited to less than 1ma. the input voltage should not exceed 200mv beyond the power supply. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. note 4: the ltc6268i/ltc6269i is guaranteed to meet specified performance from C40c to 85c. the ltc6268h/ltc6269h is guaranteed to meet specified performance from C40c to 125c. note 5: thermal resistance varies with the amount of pc board metal connected to the package. the specified values are for short traces connected to the leads. note 6: the input bias current is the average of the currents into the positive and negative input pins. t ypical measurement is for s8 package. note 7: full power bandwidth is calculated from slew rate using the following equation: fpbw = sr/(2 ? v peak ) note 8: this parameter is specified by design and/or characterization and is not tested in production. note 9: the ltc6268/ltc6269 is capable of producing peak output currents in excess of 135ma. current density limitations within the ic require the continuous current supplied by the output (sourcing or sinking) over the operating lifetime of the part be limited to under 135ma (absolute maximum). ltc 6268/ ltc 6269 62689f
7 for more information www.linear.com/ltc6268 typical performance characteristics input offset drift distribution input offset voltage vs common mode voltage input offset voltage vs supply voltage input offset voltage vs output current psrr vs frequency cmrr vs frequency input offset voltage distribution input offset voltage distribution input offset voltage vs temperature t a = 25c, unless otherwise noted. temperature (c) ?50 ?1 v os (mv) 1.5 1 0.5 0 ?0.5 2 ?30 ?10 90 110 130 150 10 5030 70 6268 g03 v s = 2.5v v cm = 1.0v v cm = 0.25v distribution (v/c) number of units 0 6268 g04 ?8 ?6 ?4 ?2 2 4 6 8 10 0 2 1 4 3 6 5 9 8 7 11 10 h-grade i-grade v s = 2.5v v cm = 0.25v v cm (v) ?2.5 ?1 v os (mv) 0.8 0.4 0.6 0 0.2 ?0.8 ?0.6 ?0.4 ?0.2 1 ?1.25 1.25 2.5 0 6268 g05 v s = 2.5v v s (v) 3 ?1 v os (mv) 0.6 0.8 0 ?0.8 ?0.6 ?0.4 ?0.2 0.2 0.4 1 3.5 5 5.5 4 4.5 6268 g06 v s ? = 0v, v s + = 3.1v to 5.25v v cm = 1v output current (ma) ?100 ?0.20 v os (mv) 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 ?80 ?60 40 60 80 100 40 0?20 20 6268 g07 v cm = 1.5v v s = 2.5v v cm = 0.25v frequency (mhz) 0.01 ?20 psrr (db) 80 60 40 20 0 100 0.1 100 1000 1 10 6268 g08 v s = 2.5v v cm = 0.25v ?psrr +psrr frequency (mhz) 0.01 0 cmrr (db) 100 80 60 40 20 120 0.1 10 100 1000 1 6268 g09 v s = 2.5v v cm = 0.25v 0 250 200 150 100 50 300 6268 g01 v s = 2.5v v cm = 0.25v ?0.4 ?0.3 0.2 0.3 0.4 0.5 0.6 ?0.2 ?01 0 0.1 v os (mv) 0 200 150 100 50 250 6268 g02 v s = 2.5v v cm = 1.5v ?0.4 ?0.3 0.2 0.3 0.4 0.5 0.6 ?0.2 ?01 0 0.1 v os (mv) ltc 6268/ ltc 6269 62689f
8 for more information www.linear.com/ltc6268 typical performance characteristics output saturation voltage vs load current (output low) output saturation voltage vs load current (output high) output short circuit current vs supply voltage input referred voltage noise wide band input referred voltage noise input bias current vs common mode voltage input bias current vs supply voltage input bias current vs temperature t a = 25c, unless otherwise noted. 0.1hz to 10hz output voltage noise ?in +in common mode voltage (v) 0.0 ?300 input bias current (fa) input bias current (fa) 300 200 v s = 5v 100 0 ?100 ?200 ?10.0 10.0 8.0 6.0 4.0 2.0 0.0 ?2.0 ?4.0 ?6.0 ?8.0 1.0 4.0 5.0 2.0 3.0 6268 g10 supply voltage (v) 3.0 ?10 input bias current (fa) ?2 ?1 ?4 ?3 ?5 ?7 ?6 ?9 ?8 0 3.5 5.0 5.5 4.0 4.5 6268 g11 v s = 3.1v to 5.25v v cm = 1.0v +in ?in temperature (c) 25 ?200 current (fa) 1400 1000 1200 800 400 600 0 200 1600 45 105 125 65 85 6268 g12 ?in +in v s = 2.5v v cm = 0.25v load current (ma) 0.0 0 output saturation voltage (mv) 160 120 40 80 200 10.0 5.0 20.0 25.0 15.0 6268 g13 v s = 2.5v v cm = 0.25v t a = ?55c t a = 25c t a = 125c load current (ma) 0.0 ?280 output saturation voltage (mv) ?40 ?120 ?200 ?240 ?80 ?160 0 5.0 20.0 25.0 10.0 15.0 6268 g14 v s = 2.5v v cm = 0.25v t a = ?55c t a = 25c t a = 125c v s = 2.5v v cm = 0.25v v s (v) 3.0 ?200 i sc (ma) 150 0 ?100 ?150 50 100 ?50 200 3.5 5.0 5.5 4.0 4.5 6268 g15 sinking sourcing t a = ?55c t a = 25c t a = 125c frequency (hz) 10k 0 voltage noise (nv/ hz) 9 8 7 6 5 4 3 2 1 10 1m 100k 6268 g16 v s = 2.5v v cm = 0.25v frequency (mhz) 0 20 40 60 80 0 voltage noise (nv/ hz) 5 4 3 2 1 6 100 6268 g17 v s = 2.5v v cm = 0.25v time (s) 0 1 2 3 4 5 6 7 8 9 ?20 voltage noise (v) 16 12 8 4 ?16 ?12 ?8 ?4 0 20 10 6268 g18 v s = 2.5v v cm = 0.25v ltc 6268/ ltc 6269 62689f
9 for more information www.linear.com/ltc6268 0.1hz to 10hz output voltage noise t a = 25c, unless otherwise noted. typical performance characteristics output impedance vs frequency harmonic distortion vs frequency harmonic distortion vs amplitude harmonic distortion vs amplitude 50mv step response 50mv step response input referred current noise gain and phase vs frequency time (s) 0 1 2 3 4 5 6 7 8 9 ?20 voltage noise (v) 16 12 8 4 ?16 ?12 ?8 ?4 0 20 10 6268 g19 v s = 2.5v v cm = 1.5v frequency (mhz) 1 10 0.1 current noise (pa/hz) 10 1 100 100 6268 g20 v s = 2.5v v cm = 0.25v frequency (mhz) 0.1 ?30 gain (db) phase 50 30 20 10 0 40 ?10 ?20 60 ?180 ?20 ?60 ?80 ?100 ?120 ?40 ?140 ?160 0 1 100 1000 10 6268 g21 v s = 2.5v v cm = 0.25v a = 1000 r l = 1k, c l = 0pf r l = 1k, c l = 10pf gain phase frequency (mhz) 0.001 0.001 output impedance () 1 0.1 10 0.01 1000 100 0.01 10 100 1000 0.1 1 6268 g22 v s = 2.5v v cm = 0.25v a v = 1 a v = 10 a v = 100 frequency (mhz) 0.1 ?140 distortion (db) ?40 ?60 ?80 ?100 ?120 ?20 10 1 6268 g23 v s = 2.5v v out = 2v p-p r l = 1k a v = 1 v cm = ?0.75v 2nd 3rd amplitude (v p-p ) 0.5 ?140 distortion (db) ?40 ?60 ?80 ?100 ?120 ?20 2 1 1.5 6268 g24 v s = 2.5v v cm = ?0.75v r l = 1k a v = 1 f o = 1mhz 2nd hd 3rd hd amplitude (v p-p ) 0.25 ?140 distortion (db) ?40 ?60 ?80 ?100 ?120 ?20 2 1 1.51.25 0.750.5 1.75 6268 g25 2nd hd 3rd hd v s = 2.5v v cm = ?0.75v r l = 1k a v = 1 f o = 10mhz a v = 1 v s = 0, 5v v cm = 0.5v, 2.5v, 4.5v r load = 1k time (ns) 0 ?30 ?20 ?10 0 v out (mv) 70 40 20 10 50 60 30 80 10 5 454035 50 252015 30 6268 g26 v cm = 0.5v v cm = 2.5v v cm = 4.5v a v = 1 v s = 0, 5v v cm = 0.5v, 2.5v, 4.5v r load = 1k, c load = 10pf time (ns) 0 ?30 ?20 ?10 0 v out (mv) 70 40 20 10 50 60 30 80 10 5 454035 50 252015 30 6268 g26a v cm = 0.5v v cm = 2.5v v cm = 4.5v ltc 6268/ ltc 6269 62689f
10 for more information www.linear.com/ltc6268 typical performance characteristics supply current vs supply voltage supply current vs shutdown voltage supply current vs shutdown voltage t a = 25c, unless otherwise noted. supply voltage (v) 3.0 0 supply current (ma) 30 15 18 21 24 27 12 9 6 3 3.5 5.0 5.5 4.0 4.5 6268 g28 t a = ?55c t a = 25c t a = 125c v s ? = 0v v cm = 1v a v = 1 shut down voltage (v) 0.0 0 supply current (ma) 25 15 20 10 5 1.5 2.0 0.5 1.0 6268 g29 v s = 0v, 5v v cm = 2.75v a v = 1 t a = ?55c t a = 25c t a = 125c shut down voltage (v) 0.0 0 supply current (ma) 25 15 20 10 5 1.5 2.0 0.5 1.0 6268 g30 v s = 0v, 3.1v v cm = 1v a v = 1 t a = ?55c t a = 25c t a = 125c large signal response time (ns) 0 ?2.5 ?3.0 v out (v) 2.0 1.5 1.0 0.5 0.0 ?0.5 ?1.0 ?2.0 ?1.5 3.0 2.5 20 80 100 40 60 6268 g27 v s = 2.5v, a v = 1, r load = 1k c load = 0pf c load = 10pf ltc 6268/ ltc 6269 62689f
11 for more information www.linear.com/ltc6268 pin functions Cin: inverting input of the amplifier. the voltage range of this pin is from v C to v + C0.5v. +in: non-inverting input. the voltage range of this pin is from v C to v + C0.5v. v + : positive power supply. total supply (v + C v C ) voltage is from 3.1 v to 5.25 v. split supplies are possible as long as the total voltage between v + and v C is between 3.1 v and 5.25. a bypass capacitor of 0.1 f should be used between v + to ground as close to the pin as possible. v C : negative power supply. normally tied to ground, it can also be tied to a voltage other than ground as long as the voltage difference between v + and v C is between 3.1v and 5.25 v. if it is not connected to ground, bypass it to ground with a capacitor of 0.1 f as close to the pin as possible. shdn, sda, sdb : active low op amp shutdown, threshold is 0.75 v above the negative supply, v C . if left unconnected, the amplifier is enabled. out: amplifier output. nc: not connected. may be used to create a guard ring around the input to guard against board leakage currents. see applications information section for more details. v ? v + d7 d6 q7 q5 q6 q3 q4 buffer i0 c0 q1 d4 q2 d5 out q9 q8 ?in +in sd esd_d2 esd_d0 esd_d1 esd_d3 input replica input replica cmos input buffer reference generation complementary input stage cascode stage 6268 bd simplified schematic ltc6268 simplified schematic diagram ltc 6268/ ltc 6269 62689f
12 for more information www.linear.com/ltc6268 operation the ltc6268 input signal range is specified from the negative supply to 0.5 v below the positive power supply, while the output can swing from rail-to-rail. the schematic above depicts a simplified schematic of the amplifier. the input pins drive a cmos buffer stage. the cmos buffer stage creates replicas of the input voltages to boot strap the protection diodes. in turn, the buffer stage drives a complementary input stage consisting of two differential amplifiers, active over different ranges of input common mode voltage. the main differential amplifier is active with input common mode voltages from the negative power supply to approximately 1.55 v below the positive supply, with the second amplifier active over the remaining range to 0.5 v below the positive supply rail. the buffer and output bias stage uses a special compensation technique ensuring stability of the op amp. the common emitter topology of output transistors q1/q2 enables the output to swing from rail-to-rail. applications information figure 1. simplified tia schematic for a trans-impedance amplifier ( tia) application such as shown in figure 1, all three of these op amp parameters, plus the value of feedback resistance r f , contribute to noise behavior in different ways, and external components and traces will add to c in . it is important to understand the impact of each parameter independently. input referred voltage noise (e n ) consists of flicker noise (or 1/ f noise), which dominates at lower frequencies, and thermal noise which dominates at higher frequencies. for ltc6268, the 1/f corner, or transition between 1/ f and thermal noise, is at 80 khz. the i n and r f contributions to input referred noise current at the minus input are relatively straight forward, while the e n contribution is amplified by the noise gain. because there is no gain resistor, the noise gain is calculated using feedback resistor (r f ) in conjunction with impedance of c in as (1 + 2 r f ? c in ? freq), which increases with frequency. all of the contributions will be limited by the closed loop bandwidth. the equivalent input current noise is shown in figures 2-5, where e n represents contribution from input referred voltage noise (e n ), i n represents contribution from input referred current noise ( i n ), and r f represents contribution from feedback resistor (r f ). tia gain (r f ) and capacitance at input (c in ) are also shown on each figure. comparing figures 2 & 3, and 4 & 5 for higher frequencies, e n dominates when c in is high (5pf) due to the amplification mentioned above while i n dominates when c in is low (1 pf). at lower frequencies, the ? + c f r f c in gnd in out 6268 f01 noise to minimize the ltc6268s noise over a broad range of applications, careful consideration has been placed on input referred voltage noise ( e n ), input referred current noise (i n ) and input capacitance c in . ltc 6268/ ltc 6269 62689f
13 for more information www.linear.com/ltc6268 r f contribution dominates for 10 k and 100 k. since wide band e n is 4.3nv/hz ( see typical performance characterit- ics), r f contribution will become a lesser factor at lower frequencies if r f is less than 1.16 k as indicated by the following equation: en / r f 4kt / r f 1 frequency (mhz) 0 0 noise density (pa/ hz) 4 3 2 1 5 60 80 100 20 40 6268 f02 total r f i n e n r f = 10k c in = 1pf c f = 0.28pf applications information figure 2 figure 3 figure 4 figure 5 frequency (hz) 0 0 noise density (pa/ hz) 4 3 2 1 5 60 80 100 20 40 6268 f04 r f = 100k c in = 1pf c f = 0.08pf total r f i n e n frequency (mhz) 0 0 noise density (pa/ hz) 4 3 2 1 5 60 80 100 20 40 6268 f05 r f = 100k c in = 5pf c f = 0.18pf total r f i n e n r f = 10k c in = 5pf c f = 0.56pf frequency (mhz) 0 0 noise density (pa/ hz) 4 3 2 1 5 60 80 100 20 40 6268 f03 total r f i n e n optimizing the bandwidth for tia application the capacitance at the inverting input node can cause amplifier stability problems if left unchecked. when the feedback around the op amp is resistive (r f ), a pole will be created with r f ||c in . this pole can create excessive phase shift and possibly oscillation. referring to figure 1, the response at the output is: r f 1 + 2 s + s 2 2 ltc 6268/ ltc 6269 62689f
14 for more information www.linear.com/ltc6268 applications information where r f is the dc gain of the tia , is the natural fre- quency of the closed loop, which can be expressed as: = 2 gbw r f (c in + c f ) is the damping factor of the loop, which can be ex- pressed as = 1 2 1 2 gbw r f (c in + c f ) ? ? ? + r f c f + c in + c f 1 + a o ? ? ? ? ? ? + 2 gbw r f c in + c f ( ) ? ? ? where c in is the total capacitance at the inverting input node of the op amp, and gbw is the gain bandwidth of the op amp. there are two regions that the system will be stable regardless of c f . the first region is when r f is less than 1/(4?c in ?gbw). in this region, the pole produced by the feedback resistor and c in is at a high frequency which does not cause stability problems. the second region is where: r f > a o 2 gbw c in where a o is the dc open loop gain of the op amp, and the pole formed by r f c in is the dominant pole. for r f between these two regions, the small capacitor c f in parallel with r f can introduce enough damping to stabilize the loop. by assuming c in >> c f , the following condition needs to be met for c f , c f > c in gbw r f the above condition implies that higher gbw will require lower feedback capacitance c f , which will have higher loop bandwidth. table 1 shows the optimal c f for r f of 10k and 100k and c in of 1pf and 5pf. table 1. min c f r f c in = 1pf c in = 5pf 10k 0.25pf 0.56pf 100k 0.08pf 0.18pf achieving higher bandwidth with higher gain tias good layout practices are essential to achieving best re - sults from a tia circuit. the following two examples show drastically different results from an ltc6268 in a 499 k tia. ( see figure 6.) the first example is with an 0603 re - sistor in a basic circuit layout. in a simple layout, without expending a lot of effort to reduce feedback capacitance, the bandwidth achieved is about 2.5 mhz. in this case, the bandwidth of the tia is limited not by the gbw of the ltc6268, but rather by the fact that the feedback capaci - tance is reducing the actual feedback impedance ( the tia gain itself) of the tia. basically, its a resistor bandwidth limitation. the impedance of the 499 k is being reduced by its own parasitic capacitance at high frequency. from the 2.5 mhz bandwidth and the 499 k low frequency gain, we can estimate the total feedback capacitance as c = 1/(2 ? 2.5mhz ? 499k) = 0.13 pf. thats fairly low, but it can be reduced further. figure 6. ltc6268 and low capacitance photodiode in a 499k tia parasitic feedback c 499k ?2.5 6268 f06 k a pd case ?2.5 pd: osi fci-125g-006 +2.5 i pd v out + ? ltc6268 ltc 6268/ ltc 6269 62689f
15 for more information www.linear.com/ltc6268 with some extra layout techniques to reduce feedback capacitance, the bandwidth can be increased. note that we are increasing the effective bandwidth of the 499 k resistance. one of the main ways to reduce capacitance is to increase the distance between the plates, in this case the plates being the two endcaps of the component resistor. for that reason, it will serve our purposes to go to a longer resistor. an 0805 is longer than an 0603, but its endcaps are also larger in area, increasing capacitance again. however , increasing distance between the endcaps is not the only way to decrease capacitance, and the extra distance between the resistor endcaps also allows the easy application of another technique to reduce feedback capacitance. a very powerful method to reduce plate to plate capacitance is to shield the e field paths that give rise to the capacitance. in this particular case, the method is to place a short ground trace between the resistor pads, near the tia output end. applications information figure 8. a normal layout at left and a field- shunting layout at right. simply adding a ground trace under the feedback resistor does much to shunt field away from the feedback side and dumps it to ground. note that the dielectric constant of fr4 and ceramic is typically 4, so most of the capacitance is in the solids and not through the air. (reduced pad size on right is not shown.) ceramic r substrate resistive element e field ? c endcap k a g ?2.5 fr4 i pd v out + ? ltc6268 e e ceramic r substrate resistive element extra gnd trace under resistor take e field to gnd, much lower c endcap 6268 f08 k a g ?2.5 fr4 i pd v out + ? ltc6268 such a ground trace shields the output field from getting to the summing node end of the resistor and effectively shunts the field to ground instead. keeping the trace close to the output end increases the output load capacitance very slightly. see figure 8 for a pictorial representation. figure 9 shows the dramatic increase in bandwidth simply by careful attention to low capacitance methods around the feedback resistance. bandwidth was raised from 2.5mhz to 11.2 mhz, a factor greater than 4. methods implemented were two: 1) minimal pad sizing. check with your board assembler for minimum acceptable pad sizing, or assemble this resistor using other means, and 2) shield the feedback capacitance using a ground trace under the feedback resistor near the output side. figure 7. frequency response of 499k tia without extra effort to reduce feedback capacitance is 2.5mhz figure 9. ltc6268 in a 499k tia with extra layout effort to reduce feedback capacitance achieves 11.2mhz bw ltc 6268/ ltc 6269 62689f
16 for more information www.linear.com/ltc6268 applications information high impedance buffer the very high input impedance of the ltc6268 makes it ideal for buffering high impedance or capacitive sources . the circuit of figure 10 shows the ltc6268 applied as a buffer, after a simple rc filter. the rlc network after the buffer acts as an absorptive filter to avoid excessive time domain reflections of the adc glitches. the 2.048 v refer - ence establishes a midpoint input zero reference voltage. the lt1395 high speed current feedback amplifier and its associated resistor network attenuate the buffered signal and render it differential by forcing the common mode to virtual ground ( the v cm voltage provided by the adc). figure 10. ltc6268 as a high-z buffer driving an lt1395 as a single-ended to differential converter into a 16-bit adc a in + a in ? ltc2269 1.8v d15 d0 v dd 1.8v ov dd ? ? ? ltc2269 16-bit 20 msps adc 6268 f10 v cm 10mhz clock clock control output drivers ognd gnd s/h 16-bit adc core ltc6655-2.048 v in v out_s v out_f gnd shdn v in v in = 2.048v 1.7v fs v ref r2 75 r1 49.9 r6 100 r7 100 r4 49.9 r10 75 r16 49.9 r17 49.9 r15 402 r13 825 r18 49.9 r11 75 r8 200 l4 100nh l3 100nh c5 .01f r14 402 r12 825 r5 49.9 r9 200 c2 10pf c3 10pf c4 100f c in 0.1f c4 0.1f l1 100nh l2 100nh +v +v r3 10m c1 22pf u1 + ? ltc6268 lt1395 u2 +v +v = 5v Cv = C5v ?v + ? ? + ? + ltc 6268/ ltc 6269 62689f
17 for more information www.linear.com/ltc6268 figure 11. sampled time domain response of the circuit of figure 10 applications information figure 11 shows the time domain response of a 10.101mhz 3v p-p input square wave, sampled at 10 msps, just 1ns slower than the waveform rate. at this rate, the waveform appears reconstructed at a rate of 1ns per sample, allowing for a more immediate view of the settling characteristics, even though each sample is really 100ns later. maintaining ultralow input bias current leakage currents into high impedance signal nodes can easily degrade measurement accuracy of fa signals. high temperature applications are especially susceptible to these issues. for humid environments, surface coating may be necessary to provide a moisture barrier. there are several factors to consider in a low input bias current circuit. at the femtoamp level, leakage sources can come from unexpected sources including adjacent signals on the pcb, both on the same layer and from internal layers, any form of contamination on the board from the assembly process or the environment, other components on the signal path and even the plastic of the device pack - age. care taken in the design of the system can mitigate these sour ces and achieve excellent performance. figure 12. example layout of inverting amplifier (or t rans-impedance) with leakage guard ring (a) (b) high-z sensor (r in ) low impedance node absorbs leakage current guard ring leakage current nc +in nc ?in v + v ? sd out ? ? no leakage current. v ?in = v grd avoid dissipating significant amounts of power in this resistor. it will generate thermal gradients with respect to the input pins and lead to thermocouple-induced error. v bias v ?in r f 6268 f12 ltc6268 s8 no solder mask over guard ring + ? guard ring ltc6268 leakage current leakage current is absorbed by ground instead of causing a measurement error. v out v + v ? high-z sensor r f v bias + ? v in r in the choice of device package should be considered because although each has the same die internally, the pin spacing and adjacent signals influence the input bias current. the ltc6268/ltc6269 is available in soic, msop, dfn and sot-23 packages. of these, the soic has been designed as the best choice for low input bias current. it has the largest lead spacing which increases the impedance of the package plastic and the pinout is such that the two input pins are isolated on the far side of the package from the other signals. the gull-wing leads on this package also allow for better cleaning of the pcb and reduced contamination-induced leakage. the other packages have advantages in size and pin count but do so by reducing the input isolation. leadless packages such as the dfn offer the minimum size but have the smallest pin spacing and may trap contaminants under the package. time (10ns/div) 6268 f11 f s = 10msps f in = 10.101mhz 0 adc outputs (counts) 60k 52k 56k 36k 44k 48k 40k 4k 8k 12k 16k 20k 24k 28k 32k 64k 440 460 480 520 540 560 580 500 ltc 6268/ ltc 6269 62689f
18 for more information www.linear.com/ltc6268 applications information the material used in the construction of the pcb can sometimes influence the leakage characteristics of the design. exotic materials such as teflon can be used to improve leakage performance in specific cases but they are generally not necessary if some basic rules are applied in the design of conventional fr4 pcbs. it is important to keep the high impedance signal path as short as possible on the board. a node with high impedance is susceptible to picking up any stray signals in the system so keeping it as short as possible reduces this effect. in some cases, it may be necessary to have a metallic shield over this por - tion of the circuit. however, metallic shielding increases capacitance. another technique for avoiding leakage paths is to cut slots in the pcb. high impedance circuits are also susceptible to electrostatic as well as electromagnetic ef - fects. the static charge carried by a person walking by the cir cuit can induce an interference on the order of 100 s of femtoamps. a metallic shield can reduce this effect as well. the layout of a high impedance input node is very important. other signals should be routed well away from this signal path and there should be no internal power planes under it. the best defense from coupling signals is distance and this includes vertically as well as on the surface. in cases where the space is limited, slotting the board around the high impedance input nodes can provide additional isola - tion and reduce the effect of contamination. in electrically noisy environments the use of driven guard rings around these nodes can be effective ( see figure 12). adding any additional components such as filters to the high imped - ance input node can increase leakage. the leakage current of a ceramic capacitor is orders of magnitude larger than the bias current of this device. any filtering will need to be done after this first stage in the signal chain. low input offset voltage the ltc6268 has a maximum offset voltage of 2.5mv (pnp region) over temperature. the low offset voltage is essential for precision applications. there are 2 different input stages that are used depending on the input common mode voltage. to increase the versatility of the ltc6268, the offset voltages are trimmed for both regions of operation. rail-to-rail output the ltc6268 has a rail-to-rail output stage that has ex - cellent output drive capability. it is capable of delivering over 40 ma of output drive current over temperature. furthermore, the output can reach within 200 mv of either rail while driving 10ma. attention must be paid to keep the junction temperature of the ic below 150c. input protection to prevent breakdown of internal devices in the input stage, the two op amp inputs should not be separated by more than 2.0v. to help protect the input stage, internal circuitry will engage automatically if the inputs are separated by >2.0v and input currents will begin to flow. in all cases, care should be taken so that these currents remain less than 1 ma. additionally, if only one input is driven, inter - nal cir cuitry will prevent any breakdown condition under transient conditions. the worst-case differential input voltage usually occurs when the + input is driven and the output is accidentally shorted to ground while in a unity gain configuration. ltc 6268/ ltc 6269 62689f
19 for more information www.linear.com/ltc6268 applications information esd esd protection devices can be seen in the simplified sche- matic. the + in and C in pins use a sophisticated method of esd protection that incorporates a total of 4 reverse- biased diodes connected as 2 series diodes to each rail. to maintain extremely low input bias currents, the center node of each of these series diode chains is driven by a buffered copy of the input voltage. this maintains the two diodes connected directly to the input pins at low reverse bias, minimizing leakage current of these esd diodes to the input pins. the remaining pins have traditional esd protection, using reverse- biased esd diodes connected to each power supply rail. care should be taken to make sure that the voltages on these pins do not exceed the supply voltages by more than 100 mv or these diodes will begin to conduct large amounts of current. shutdown the ltc6268s 6, ltc6268 s 8, and ltc6269dd have shdn pins that can shut down the amplifier to less than 1.2ma supply current per amplifier. the shdn pin voltage needs to be within 0.75 v of v C for the amplifier to shut down. during shutdown, the output will be in a high output re- sistance state , so the ltc6268 is suitable for multiplexer applications. the internal circuitry is kept in a low current active state for fast recovery. when left floating, the shdn pin is internally pulled up to the positive supply and the amplifier is enabled. ltc 6268/ ltc 6269 62689f
20 for more information www.linear.com/ltc6268 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 1.50 ? 1.75 (note 4) 2.80 bsc 0.30 ? 0.45 6 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) s6 tsot-23 0302 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) ltc 6268/ ltc 6269 62689f
21 for more information www.linear.com/ltc6268 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) so8 rev g 0212 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) 4. pin 1 can be bevel edge or a dimple s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610 rev g) ltc 6268/ ltc 6269 62689f
22 for more information www.linear.com/ltc6268 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8e) 0213 rev k 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 8 1 bottom view of exposed pad option 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 1.68 (.066) 1.88 (.074) 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.889 0.127 (.035 .005) recommended solder pad layout 0.65 (.0256) bsc 0.42 0.038 (.0165 .0015) typ 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref ms8e package 8-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1662 rev k) ltc 6268/ ltc 6269 62689f
23 for more information www.linear.com/ltc6268 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 notch r = 0.20 or 0.35 45 chamfer ltc 6268/ ltc 6269 62689f
24 for more information www.linear.com/ltc6268 ? linear technology corporation 2014 lt 0914 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc6268 related parts typical application part number description comments op amps ltc6244 dual 50mhz, low noise, rail-to-rail, cmos op amp unity gain stable, 1pa input bias current, 100v max offset. ltc6240/ltc6241/ ltc6242 18mhz, low noise, rail-to-rail output, cmos op amp 18mhz gbw, 0.2pa input current, 125v max offset. ltc6252/ltc6253/ ltc6254 720mhz, 3.5ma power efficient rail-to-rail i/o op amp 720mhz gbw, unity gain stable, low noise ltc6246/ltc6247/ ltc6248 180mhz, 1ma power efficient rail-to-rail i/o op amps 180mhz gbw, unity gain stable, low noise lt1818 400mhz, 2500v/s, 9ma single operational amplifier unity gain stable, 6nv/ hz unity gain stable lt6230 215mhz, rail-to-rail output, 1.1nv/hz , 3.5ma op amp family 350v max offset voltage, 3v to 12.6v supply lt6411 650mhz differential adc driver/dual selectable amplifier sr 3300v/s, 6ns 0.1% settling. sar adc ltc2376-18/ ltc2377-18/ ltc2378-18/ ltc2379-18 18-bit, 250ksps to 1.6msps, low power sar adc, 102db snr 18mw at 1.6msps, 3.4w at 250sps, C126db thd. ltc6268 as a high-z buffer driving an lt1395 as a single-ended to differential converter into a 16-bit adc reconstructed sampled time domain response of above circuit a in + a in ? ltc2269 1.8v d15 d0 v dd 1.8v ov dd ? ? ? ltc2269 16-bit 20 msps adc 6268 ta03 v cm 10mhz clock clock control output drivers ognd gnd 16-bit adc core ltc6655-2.048 v in v out_s v out_f gnd shdn v in v in = 2.048v 1.7v fs v ref r2 75 r1 49.9 r6 100 r7 100 r4 49.9 r10 75 r16 49.9 r17 49.9 r15 402 r13 825 r18 49.9 r11 75 r8 200 l4 100nh l3 100nh c5 .01f r14 402 r12 825 r5 49.9 r9 200 c2 10pf c3 10pf c4 100f c in 0.1f c4 0.1f l1 100nh l2 100nh +v +v r3 10m c1 22pf u1 + ? ltc6268 lt1395 u2 +v +v = 5v Cv = C5v ?v + ? ? + ? + s/h time (10ns/div) 6268 f11 f s = 10msps f in = 10.101mhz 0 adc outputs (counts) 60k 52k 56k 36k 44k 48k 40k 4k 8k 12k 16k 20k 24k 28k 32k 64k 440 460 480 520 540 560 580 500 ltc 6268/ ltc 6269 62689f

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